1. Field of the Invention
This invention relates to the field of memory arrays and in particular to a circuitry for providing a XNOR/XOR decoding for on-chip redundant memory.
2. Prior Art
An arrayed memory, such as a random access memory (RAM) or an erasable programmable read-only-memory (EPROM), is generally comprised of an array of binary elements arranged in a matrix of rows and columns. Addresses associated with the array access memory locations within the array. Typically, decoders are coupled to the memory to provide the decoding of the address signals. The design and manufacture of various semiconductor memories, where memory cells are arranged in an array, are well-known in the prior art.
In the manufacture of such memory arrays, processing defects often randomly occur across the memory chip. In most instances, these memory chips are fully functional except for a single or a small number of row or column containing a defective cell. In order not to scrap a chip for having a single or a small number of defects, defect tolerant memory devices have been devised in which a redundant row and/or column of cells is substituted for a selected row and/or column containing the defective cell(s).
For example, in U.S. Pat. No. 3,659,275, a system is described in which at least one read-only-memory having permanently stored data therein is accessed in parallel with a correction or redundant memory element. U.S. Pat. Nos. 3,735,368 a monolithic memory is constructed of components which contain defective bit cells. In U.S. Pat. Nos. 3,753,244 and 3,753,235 teach a redundancy scheme where redundancy is provided by having an extra line of cells on the chip together with a defective address store. A comparator circuit is provided for disabling a defective line of cells and replacing it with the extra line of cells in a technique of pre-wired substrates for monolithic memories. In U.S. Pat. No. 4,051,354, a fault tolerant cell addressable array having one or more superfluous rows and/or columns of cells is held in reserve. The memory chips with faulty cells are corrected by programming the memory with the cell addresses of the faulty cell locations.
More recently, a redundant memory circuit for a memory array in which the memory has a preselected number of rows or columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified address associated therewith and redundant decoders coupled thereto is taught in U.S. Pat. No. 4,250,570. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith. The programming of the decoders is achieved by the use of fusible links, wherein the address decoding is achieved by open circuiting selected fusible links.
An improved addressing scheme for single chip memories which includes a plurality of redundant lines and associated cells is taught in U.S. Pat. Nos. 4,358,833 and 4,441,170. Aside from fusible links, other schemes are known in the prior art for providing the programming of the decoders to provide redundancy. That is, once the defective row and/or column addresses are known, then the redundant row and/or column decoders must be programmed to replace the defective line.
Further, another scheme for providing redundancy is achieved by the use of a content addressable memory (CAM). A content addressable memory provides for storing the addresses of defective locations of the main memory array. One such defect tolerant memory system using a CAM is taught in U.S. Pat. No. 3,633,175. However, more recently semiconductor memory devices utilize redundancy schemes where the redundancy elements are similar to the cells used in the main memory. That is, for an EPROM semiconductor memory, EPROM cells are used for redundant memory also. Instead of fusible links, actual memory cells are used to provide the programming.
In redundancy circuits using CAMs to program the redundant addresses, the decoded outputs from the CAMs are typically coupled together for activating the respective redundant memory line. Gating means, such as a NOR gate, is used to combine the outputs from the CAMs. The present invention utilizes a specialized XNOR (exclusive NOR)/XOR exclusive OR) decoding circuit for accessing redundant memory.